1. Field of the Invention
The present invention relates generally to a network interface card, and more particularly, to a network interface card for reducing the number of interrupts generated in an Ethernet network and a method of generating interrupts.
2. Description of the Related Art
To improve the performance of a controller used in a gigabit Ethernet network, which is up to 10 times faster than a general 100 Mbps Ethernet network, it is necessary to optimize the transmission of interrupts, which require a considerable amount of processing time in data transmission. By reducing the number of interrupts when data are processed, the number of overheads to be processed is reduced. Thus, the performance of the controller may be improved.
A network interface card (NIC) is installed in a personal computer of a user to establish an interface connection to an Ethernet LAN (Local Area Network). The NIC has a controller and a transceiver that enable the user to use the Ethernet LAN. It is the controller that has an influence upon the performance of the NIC. The controller includes a bus interface unit for interfacing with the personal computer, a direct memory access (DMA) unit for writing to or reading from a memory, and a media access control core for processing of a protocol of the Ethernet.
FIG. 1 shows the operation of a controller of a network interface card (NIC).
Referring to FIG. 1, a network interface card (NIC) 100 includes a controller 110 and a transceiver 120. The controller 110 includes a bus interface unit 111, a direct memory access (DMA) unit 113, and a media access control (MAC) core 115.
Hereinafter, the transceiving of data of the NIC 100 will be described with reference to FIG. 1.
A data frame DF to be transmitted is sent to a device driver 150 through an upper layer protocol (ULP) of an operating system (OS), e.g., a transmission control protocol/Internet protocol (TCP/IP) or a user datagram protocol (UDP). Here, the device driver 150 is software that drives the NIC 100 (step (1)).
The device driver 150 sends the data frame DF to a memory region which the DMA unit 113 of the controller 110 accesses, e.g., a first memory Tx Queue 130 (step (2)). Then, the device driver 150 sends a transmission command to the controller 110 (step (3)).
The controller 110, which receives the transmission command, tests the first memory Tx Queue 130 by using the DMA unit 113 and transfers the data frame DF into itself (step (4)), and transmits the data frame DF, which is processed in the controller 110, to an external network (not shown) (step (5)).
To transmit data to the external network, the MAC core 115 in the controller 110 forms Ethernet frames by using the data.
When the data frame DF is received, the data frame DF is processed inversely to the transmission process. To receive the data frame DF, the device driver 150 allocates a second memory Rx Queue 140 in which a received data frame DF will be stored and informs the controller 110 when data frame DF is stored in the second memory Rx Queue 140.
When the data frame DF is received by the transceiver 120 of the NIC 100, the MAC core 115 checks whether the data frame DF is effective (step (a)).
After the MAC core 115 determines whether the data frame DF is received, the data frame DF is sent to the DMA unit 113. The DMA unit 113 transmits a received data frame DF to the second memory Rx Queue 140 (step (b)). After transmission of the data frame DF is completed, the DMA unit 113 informs the device driver 150 that it is ready to transmit the received data frame DF by generating an interrupt (INTS) (step (c)).
The interrupt INTS generated in the NIC 100 is processed by the OS and sent to the device driver 150 (step (d)). After the device driver 150 receives the interrupt INTS, it tests the second memory Rx Queue 140, searches for the received data frame DF (step (e)), and transmits the received data frame DF to the upper layer protocol (step (f)).
In these steps, since the MAC core 115 or the transceiver 120 does not store the data frame DF to be transeived, the performance of transeceiving depends on an operation of the DMA unit 113 or the device driver 150.
That is, if delays occur when the DMA unit 113 writes to or reads from the first memory Tx Queue 130 or the second memory Rx Queue 140, the time taken for transmission of one data frame DF is delayed, thus the performance of the NIC 100 is degraded.
However, the most important factor to the performance of transceiving of the data frame DF is an operation time of the device driver 150. The operation of the DMA unit 113 is performed by hardware, and thus overheads occurring therein have little influence on the performance of the NIC 100 compared to the device driver 150 that operates by software. Therefore, it is necessary to optimize the operation of the DMA unit 113 to process the data frame DF with minimum operations of the device driver 150 so that the performance of the controller 110 of the NIC 100 can be improved.
The transmission of the interrupt INTS occupies most of the time necessary for the transmission of the data frame DF. After operation of the DMA unit 113 is completed, the interrupt INTS is generated and is firstly processed by the OS. After the OS senses the generated interrupt INTS, the OS stops its operation and starts performing a process routine of the interrupt INTS. The process routine of interrupt INTS searches for, a program that will process the generated interrupt INTS and is performed by the device driver 150. That is, the process routine of the interrupt INTS includes complicated steps, and the steps are processed by software including the OS. Thus, the process routine of the interrupt INTS needs considerable time. If the number of interrupts INTS increases, a short period of time is required for a central processing unit (CPU) to process a user's task, and thus the performance of the entire system is degraded accordingly. Therefore, the performance of the entire system can be improved by processing as much data as possible by a single generation of an interrupt INTS.
FIG. 2 is a conceptual view of a conventional method of generating interrupts having delays.
In the conventional method of generating interrupts having delays, if interrupts have to be generated after a first data frame DF1 is received, the interrupts are generated after a time delay TD.
Firstly, as shown in sequence (i), data frames DF1 to DF3 are received. The time delay TD is estimated in response to the first data frame DF1. The time delay TD is stored in a control and status register (CSR) in the NIC 100 (not shown) so that the device driver 150 can control the time delay TD. The time delay TD is longer than the time necessary for receiving one data frame DF.
Even though the first data frame DF1 is received, the interrupt INTS is generated after the time delay TD. Since the received data frames DF1 and DF2 are sent to the system by the DMA unit 113 during the time delay TD, more data frames DF can be transmitted by a single generation of the interrupt.
Also, as shown in sequence (ii) of FIG. 2, the first and second data frames DF1 and DF2 can be processed by generating an interrupt once, thus it is not necessary to generate an interrupt INTS for the second data frame DF2. Here, “TP” denotes a time delay TD from generation of the interrupt INTS to calling of the process routine of the interrupt INTS from the device driver 115.
FIG. 3 is a conceptual view of another conventional method of generating interrupts having a time delay TD.
In this method, when the predetermined number of data frames DF is received, the interrupts are generated before the time delay TD is passed. Here, the maximum number of data frames DF to be received, e.g., N, is stored in the CSR and is controlled.
The device driver 150 determines whether the number of data frames DF is equal to N if the time delay TD has not passed. Here, N is smaller than the number of data frames DF that can fill the second memory Rx Queue 140 before the time delay TD is passed.
If the number of data frames DF equals N before the time delay TD is passed, the interrupt INTS is generated. If the time delay TD has passed before the number of data frames DF equals N, the interrupt INTS is also generated.
As shown in FIG. 3, if the data frame DF, e.g., data frames DF1-DF4, of the predetermined number (here, 4) is received before the time delay TD is passed, the interrupt INTS is generated so that it is possible to prevent the data frame DF from being retained without being processed.
However, if a time interval between the data frames is long, the time necessary for processing the first data frame is lengthened.